1. Technical Field
The present disclosure relates to the field of integrated circuits. The present disclosure relates more particularly to integrated circuits in printers.
2. Description of the Related Art
Metal interconnections are a standard feature of integrated circuits. Integrated circuits typically include a monocrystalline semiconductor substrate on which transistors are formed. Source and drain regions of the transistors are formed in the semiconductor substrate and a gate electrode is formed above the semiconductor substrate. A series of metal layers are formed above the semiconductor substrate. Metal tracks are formed in each metal layer. The first metal layer is typically called metal 1 with the next metal layer above that being called metal 2 and so forth. The metal layers are patterned to form metal tracks. Vias are formed in the dielectric materials separating metal layers so that metal tracks from one metal layer can be electrically connected to metal tracks in a lower or higher metal layer. Contact vias are also made to contact the source drain and gate electrodes of the transistors to electrically connect them to the metal tracks.
In a typical metal interconnection, a metal track of a first metal layer is electrically connected to a metal track of a second metal layer. After the first metal track is formed, a dielectric material is deposited on the first metal layer. The dielectric layer is then etched in a selected location to open a via to the first metal layer. The second metal layer is then deposited, patterned, and etched to form metal tracks in the second metal layer. When second metal layer is deposited, the via is filled with the second metal which acts as a contact via to the metal tracks formed by the first metal layer. Typically a thin barrier layer, or an adhesion layer, will be deposited just prior to the deposition of the second metal layer. The barrier layer overlies the dielectric layer and lines the inner walls of the via formed in the dielectric layer. The barrier layer also contacts the exposed portion of the first metal layer. After the barrier layer has been deposited, the second metal layer is then deposited, entirely filling the rest of the via and forming a metal layer on top of the insulating layer. The metal layer and the barrier layer are subsequently patterned and etched to form the desired metal tracks and interconnections.
FIG. 1A illustrates a conventional metal interconnection 20. A first metal track 22 is formed of metal 1. The first metal track 22 is, for example, AlCu. A dielectric layer 24 is then formed on the first metal track 22. The dielectric layer 24 may include multiple layers including silicon dioxide, silicon nitride, phosphor-silicate glass, or spin-on glass. The dielectric layer 24 has been etched to expose a portion of the metal track 22. A Ta barrier layer, for example 500 Å thick, has been deposited on the dielectric layer 24 and covers the sidewalls of the dielectric layer 24 as well as the exposed portion of the first metal track 22. A second metal 28 layer is deposited on top of the Ta layer. The metal layer 28 is, for example, gold, and is 3.7 kÅ thick. A photoresist layer 30 has been formed on top of the metal layer 28. The photoresist layer 30 has been patterned to form a mask in the desired pattern of the metal tracks which will be formed of the metal layer 28 and the barrier layer 26.
In FIG. 1B, the second metal layer 28 has been subjected to an isotropic wet metal etch. The wet metal etch etches the gold layer 28 outside of the photoresist layer 30. Because an isotopic etch was used, a portion of the gold metal layer 28 was undercut below the photoresist to form an overhang.
In FIG. 1C the Ta layer 26 is also subjected to an isotropic wet metal etch. The Ta layer 26 is etched outside of the photoresist layer 30 and the gold layer 28. Because an isotopic etch was used, a small portion of the Ta layer 26 is also etched under the edge of the gold layer 28. In FIG. 1D, the photoresist layer 30 has been stripped away. After the photoresist layer 30 is stripped away, a spin dry process is performed to dry the integrated circuit.
As discussed above, the top metal layer 28 is typically made of gold because it does not corrode easily and adds excellent adherence properties to the photoresist layer so that the metal layers can be etched as a single stack with the photoresist present. Gold also has other benefits of being an excellent conductor of both electricity and heat. The gold can rapidly transfer heat away from the heater for the Ta layer 26 and can also provide good electrical coupling.
Unfortunately, gold has recently become extremely expensive, and with the rising gold prices it is desirable to use another metal besides gold for the upper layer 28. Unfortunately, simply substituting another metal layer for gold cannot easily be done and several difficulties are encountered if the current process is used and another metal is merely substituted in place of the gold layer 28.
The use of a Ta alloy, such as tantalum silicon oxide as a resistor in the heater section of an ink jet printer, is well known in the art and is described for example in U.S. Patent Publication 2005/0052501. In addition, the use of gold as a top metal layer as part of a nozzle for an ink jet printer is described in various issued U.S. patents and other patent publications including U.S. Pat. No. 7,881,594 and U.S. Patent Publication 2010/0163116. Any reference to Ta herein therefore includes alloys thereof and structures that can act as resistors.